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- * Analysis of electronic scheme
- * by Cellular Logic Operations
- * Frans Groen TU-Delft
- *
- @CORSHA * correct the image for shading
- doff * display off
- bcop 1,8 * copy the thresholded image
- bcop 1,6 * original in green
- inv 6 * after inversion
- *
- * separation of drawing and text
- *
- *
- * fill small holes
- bcop 8,7,B,B * copy bitplane
- don
- erosion 1,8,4,0,B * erode small holes away
- prop 511,8,7,8,0,B * propagate for what remains
- inv 8 * cleaned drawing in red
- don,4 * multi-bitplane display on
- bcopy 8,5,B,B * save original in b5
- doff * display off
- *
- * make skeleton
- skelet 511,8,1,B * skeleton in b8
- don * single bitplane display
- bcopy 8,4 * save skeleton in b4
- *
- * shave skeleton
- bcopy 8,7,B,B * copy in b7
- -skelet 16,7,1,B * remove strokes of length 16
- exor 8,7,7,B * find strokes
- vertices 8,0,B * vertices in bitplane 3
- dilation 1,8,8,0,B * enlarge vertices
- propag 511,8,7,8,0,B * propagate vertices in strokes
- exor 4,8,8,B * cleaned object in b8
- bcopy 8,4 * save in b4
- *
- * separate text based upon vertices in
- * the skeleton with removed strokes
- *
- bcopy 8,7 * copy for propagation mask
- vertices 8,0,B * find vertices
- propag 511,8,7,8,0,B * propagate vertices in skeleton
- bcop 8,4,B,B * save cleaned skeleton in b4
- propag 511,8,5,8,0,B * propagate skeleton in drawing
- doff * display off
- reset 7 * reset for display
- don,4 * multi-bitplane display
- bcop 8,5 * save original in b5
- *doff * display off
- *
- *analyse objects
- *capacitors : big objects
- bcop 5,6 * original in b8
- ero 4,6,4 * find capacitors
- prop 4,6,5,8,0,B * propagate back
- * capacitors in b6
- *resistors : objects enclosing small holes
- don,4
- inv 5,B * invert
- bcop 5,7 * original in b7
- ero 5,7 * erode 5 times
- propag 511,7,5,8,0,B * find what remains
- exor 5,7,7,B * find what disappears
- * resistors in b7
- * opamps
- bcop 5,8
- erosion 7,8,8,0,B * erode 7 times
- propag 511,8,5,8,0,B * find what remains
- exor 5,8,8,B * and what disappears
- exor 7,8,8,B * removes the resistors
- doff
- * opamps in b8
- * finds location of components in scheme
- * extend opamps
- dilation 2,8,6,0,B * extend opamps
- bcopy 8,1,B,B * save seed bitplane
- propag 3,8,4,6,0,B * propagate in skeleton
- or 1,8,8,B * or seed bitplane
- bcopy 8,1,B,B * opamps in b1
- * extend resistors
- dilation 2,7,6,0,B * extend resistors
- bcopy 7,2,B,B * save seed bitplane
- propag 3,7,4,6,0,B * propagate in skeleton
- or 2,7,7,B * or seed bitplane
- bcopy 7,2,B,B * resistors in b2
- * extend capacitors
- bcopy 6,3,B,B * save seed bitplane
- propag 3,6,4,6,0,B * propagate capacitors in skeleton
- or 3,6,6,B * or seed bitplane
- don,4 * multi-bitplane display on
- bcopy 6,3,B,B * capacitors in b3
- * determine endpoints and branchpoints
- * find scheme without components
- bcop 4,8 * get cleaned drawing (b4)
- inv 8 * invert
- or 1,8,8 * get rid of opamps
- or 2,8,8 * resistors
- or 3,8,8 * capacitors
- inv 8 * drawing without components
- bcopy 8,6 * copy in b6 for vertices
- bcopy 8,7 * copy in b7 for endpixels
- * find endpixels of the components
- endpix 7,0,B * find endpixels
- dilation 2,7,6,0,B * extend endpixels
- * find vertices
- vertices 6,0,B
- dilation 2,6,6,0,B
- *
- * color assignment
- * lines : grey resistors : blue
- * endpixels: yellow capacitors : green
- * vertices : purple opamps : red
- *dilate lines because of low_res display
- dilation 1,8,6,0,B
- or 6,8,8
- or 7,8,8 * lines : grey 876.....
- exor 8,6,6 * vertices : purple 87......
- exor 8,7,7 * endpixels: yellow 8.6.....
- * insert components
- or 1,8,8 * opamps : red 8......1
- or 2,7,7 * resistors: blue .7....2.
- or 3,6,6 * capacitors: green ..6..3..
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